1. Field of the Invention
The present invention relates to a clock generator, and more particularly, to a programmable non-overlap clock generator that generates clock signals not logically active at the same time.
2. Description of the Prior Art
A shift register circuit is conventionally used to shift data through serially connected registers or latches. FIG. 1A shows a schematic diagram illustrating a typical shift register circuit 10 consisting of two serially connected registers DL1 and DL2, and FIG. 1B shows timing diagrams of the critical signals of FIG. 1A. A data input signal data2 is shifted from an input terminal Din of the first latch DL1 to an intermediate terminal Dint of the second latch DL2 at time t1 when a first clock signal phi1 is active (e.g., having a logic high level). The shifted data signal data2 is subsequently shifted from the intermediate terminal Dint to an output terminal Dout of the second latch DL2 at time t2 when a second clock signal phi2 is active (e.g., having a logic high level).
However, there are some parasitic capacitors and parasitic resistors caused by the material of the wiring in the shift register circuit 10, especially in shift register circuits implemented in an integrated circuit chip. FIG. 2A shows a schematic diagram illustrating a shift register circuit 20 with a parasitic capacitor C1 and a parasitic resistor R1 modeling the wire loading on the clock signal phi2. In this figure, the pertinent signals and components that are not changed in appearance from the arrangement of FIG. 1A are labeled with the same reference numerals. FIG. 2B shows timing diagrams of critical signals of FIG. 2A.
Referring to FIG. 2A, the clock signal phi2 is thus delayed due to the wire loading thereon, thereby generating a delayed clock signal phi2D inputting to the clock input terminal of the second latch DL2.
Referring now to FIG. 2B, the data input signal data2 is shifted from the input terminal Din of the first latch DL1 to the intermediate terminal Dint of the second latch DL2 at time t1 when the first clock signal phi1 is active (e.g., having a logic high level). At the same time, the delay clock signal phi2D remains active at its logic high level, therefore also shifting the data signal data2 to the output terminal Dout of the second latch DL2. Consequently, a preceding data signal datal, which is presumed to be at the output terminal Dout of the second latch DL2, is no longer there, and an unwanted data (i.e., the data signal data2 in this case) is thus retrieved. This situation is typically referred to as a race condition.
In order to overcome the aforementioned race condition, a non-overlap clock generator is disclosed to provide non-overlap clock signals. FIG. 3A schematically shows a diagram illustrating the non-overlap clock generator 30, whose output signals, i.e., the first clock signal phi1 and the second clock signal phi2, are shown in FIG. 3B. Owing to the guard band 31 between the non-overlap clock signals phi1 and phi2, it is thus guaranteed that the delayed clock signal phi2D does not overlap the first clock signal phi1, thereby preventing the race condition. Specifically, the data signal data2 is shifted from the input terminal Din of the first latch DL1 to the intermediate terminal Dint of the second latch DL2 at time t1. The output terminal Dout of the second latch DL2 has the data signal datal until the delayed clock signal phi2D becomes active at time t2.
This non-overlap clock generator 30 primarily includes two standard NAND gates 301 and 302, and two delay components 303 and 304, cross-coupled as shown in FIG. 3A. FIG. 3C shows timing diagrams of some pertinent signals of FIG. 3A. The non-overlap space d in the non-overlap clock generator 30 is determined by both the delay time d1 of the delay component 304, and the delay time d2 of the NAND gate 302. Similarly, another non-overlap space 32 is determined by both the delay time of the delay component 303, and the delay time of the NAND gate 301. Since the delay time d2 is typically fixed by the intrinsic delayed and the loading of the NAND gate 301 or 302, therefore a suitable non-overlap space d is generally attained by adjusting the delay time d1 of the delay component 303 or 304. The selection of the delay time d1 is crucial for the following reasons. If it is too small, the race condition will occur and cause circuit malfunction. On the other hand, if a large non-overlap is chosen to guarantee that no race condition occurs, the performance of the chip will be unfortunately degraded due to the fact that the active states of the signals phi1 and phi2 are decreased. If the non-overlap space is increased without scarifying the active region of the clock signals phi1 and phi2, then the total period of the clock signals phi1 and phi2 should be increased, thereby slowing down the clock signals phi1, phi2, and degrading their performance. Moreover, because the delay time d1 determined by the two delay components 303 and 304 of the non-overlap clock generator 30 in FIG. 3A has a fixed value, therefore the non-overlap space can not be changed after the chip is fabricated. Another non-overlap clock generator 30 with different non-overlap space should be redesigned and fabricated when a different application is required, thereby wasting time and money.